Verisity Simplifies the Adoption of Proven 10X SoC Verification Processes

Verisity Delivers Pre-packaged Best Practices Coupled with New Technology for SoC-Level Verification
Technical Announcement -- For a business view of this announcement, see Verisity press release titled "Verisity's sVM Simplifies the Adoption of Proven 10x SoC Verification Processes," dated Sept 15, 2003.

sVM provides productivity gains greater than 10x in the composition of SoC and system-level verification environments by raising the level of abstraction to the sequence level (combinations of transactions). In addition, multi-channel constraint solving and generation makes it possible to achieve the same coverage goals in one-tenth the number of verification cycles as compared to directed testing or other customized methods.

sVM-based environments provide for the generation of realistic, interdependent system scenarios using third-generation constraint-solver technology to fully meet coverage goals. sVM leverages the combination of new technology in Specman Elite with new libraries that include multi-channel and layered (hierarchical) sequences, a register model package, the Visualization Toolkit(TM) and other verification building blocks. In addition, Verisity also today announced eAnalyzer(TM), a static analysis and verification methodology compliance system that aids engineers in codifying Verisity's e Reuse Methodology (eRM(TM)) and sVM, thus enabling verification component reuse, and easy creation of highly automated, high-quality, consistent chip and system-level verification environments. (See related release "Verisity Launches eAnalyzer," dated September 15, 2003.)

Today's announcements represent another major step forward for Verisity's Verification Process Automation (VPA) strategy, going well beyond language and testbench toward automating and simplifying the increasingly complex process from executable test plans to verification closure. Verisity's VPA solutions combine pre-packaged, proven best practices with automation, analyses, and libraries in a form that can be readily adopted by the mainstream engineering community. In contrast to verification infrastructure (e.g., simulators) that now have limited potential for performance improvements, VPA solutions offer the potential to dramatically shorten the most time consuming verification activities by a factor of ten.

sVM - Beyond Reuse

sVM was developed based on the huge success of Verisity's e Reuse Methodology (eRM) and extends eRM's applicability to meet the unique and complex needs for chip, SoC and system-level verification. sVM goes beyond just verification reuse by providing a methodology covering the complete verification process.

"We encapsulated best practices for verification reuse into eRM just over a year ago and it has been widely accepted within our customer base," said Steve Glaser, vice president of corporate marketing and business development for Verisity. "With sVM, we've taken best practices developed with our high-end customers doing SoC-level verification, and created a widely adoptable companion methodology to the eRM. sVM and its enabling technologies deliver pre-packaged expertise and 10x automation power to the broader community."

Addressing the Shortage of SoC Verification Expertise

The evolution of increased chip-level verification complexity combined with limited verification expertise requires VPA solutions that go well beyond simulation infrastructure or variations of existing design and verification languages. With sVM and its associated technology enhancements, Verisity provides a complete "out-of-the-box" solution that increases verification productivity and proliferates best practices. Verification expertise has become so specialized, that companies are increasingly facing a shortage of engineers who can effectively define and manage the verification process. sVM simplifies the adoption of proven SoC verification methodologies for a much broader range of engineers.

Multi-Channel, SoC-level Generation and Algorithm Scalability Enhancements

A supporting technology of sVM is multi-channel and layered sequence generation. Multi-channel generation enables a new level of verification automation at the SoC and system levels. Automated verification of SoCs requires a methodology and verification architecture that mirrors the architecture of the design itself. Typically, SoCs have multiple I/Os and multiple on-chip busses linking many IP components. Such devices need to be thoroughly exercised simultaneously from all possible interfaces to control and receive data. This requires embedding of generators, checkers and monitors for each channel, as well as multi-channel constraint solving, synchronization and coordination. This is the only proven way to introduce all possible scenarios and reach all corner cases at the SoC level. Unfortunately, this is very difficult without new abstractions and automated support for specifying and generating system-level scenarios using independent yet coordinated sequences (groups of transactions). It also requires specialized algorithms to ensure scalability of capacity, performance and time-to-verification closure.

"The process of applying random stimulus generation for SoC and chip-level verification has been fairly limited in the past due to the difficulty in creating realistic system-level scenarios and the limited scalability of verification algorithms," said Mike Stellfox, worldwide director of consulting and product engineering for Verisity. "With Specman Elite's new multi-channel sequence generation technology, many leading-edge customers are now able to realize significant gains in efficiency for full-chip verification. This new technology automates and simplifies the process of creating verification environments and stimulating their complete chip with critical, real-world traffic. Multi-channel sequence generation is clearly a key enabling technology for automating and proliferating the sVM process for SoC and chip-level verification."

sVM coupled with highly scaleable, multi-channel generation technology also leverages environments built in multiple levels of hierarchy. sVM's multi-channel sequences also use block-level sequence stimulus, enabling them to be automatically combined, synchronized, and coordinated at the system level to simulate real-world conditions. This allows simultaneous and coordinated stimulation of the device through all possible channels, with maximum intelligence and efficiency of verification cycles. Using multi-channel generation, Verisity's leading-edge customers have experienced more than a 10x increase in the automation power applied at the SoC and system level. By raising the level of abstraction to the sequence level (combinations of transactions), it now takes one-tenth the time to compose and bring up SoC-level verification environments. In addition, multi-channel constraint solving and generation requires one-tenth the number of verification cycles to achieve the same coverage goals versus directed testing or other customized methods.

Register Modeling

sVM also provides support for powerful register modeling and automated device configuration generation using a new register package. sVM's register package provides a way to model, generate and check the configuration for the entire chip or SoC. Today's complex chips are highly programmable and engineers need to verify that programmability. sVM's register package provides the ability to model all device registers easily and efficiently, automatically generates configuration sequences, and automates much of the checking and coverage of register access and the device state. It also allows users to map registers into address spaces, and handle address spaces in general. Ultimately, by incorporating the register package, all verification components will use the same interface, which dramatically shortens the time it takes for verification environment creation.

Visualization Toolkit

To support the analysis portion of sVM, the Visualization Toolkit (VT) has been upgraded to support key aspects of the SoC-level verification process and environment. VT provides visualization and debugging of the multi-channel sequence generation transaction interactions, which greatly simplifies understanding and debugging chip-level environments. It also includes a rich API for creating customized visualization aids.

Pricing and Availability

The updated library package which includes multi-channel generation technology, the register model package and the new Visualization Tookit, and documentation, will be available with the full release of Specman Elite v4.3 scheduled for October 2003. Limited release versions are available today. All technology enhancements and sVM will be provided at no charge to Specman Elite customers.

About Verisity

Verisity, Ltd. (Nasdaq:VRST), is the leading supplier of process automation solutions for the functional verification market. The company addresses customers' critical business issues with its market-leading software and intellectual property (IP) that effectively and efficiently verify the design of electronic systems and complex integrated circuits for the communications, computing, and consumer electronics global markets. Verisity's Specman Elite(R) verification process automation solution automates manual processes and detects critical flaws in hardware designs enabling delivery of the highest quality products and accelerating time to market. The company's strong market presence is driven by its proven technology, methodology, and solid strategic partnerships and programs. Verisity's customer list includes leading companies in all strategic technology sectors. Verisity is a global organization with offices throughout Asia, Europe, and North America. Verisity's principal executive offices are located in Mountain View, California, with its principal research and development offices located in Rosh Ha'ain, Israel. For more information, visit www.verisity.com.

Verisity, the Verisity logo, eAnalyzer, eRM, Specman Elite, sVM and Visualization Toolkit are either registered trademarks or trademarks of Verisity Design, Inc. in the United States and/or other jurisdictions. All other trademarks are the property of their respective holders.

CONTACT: Verisity Design, Inc.
             Jennifer Bilsey, 650-934-6823
             jen@verisity.com